1. Field of the Invention
The present invention relates to a semiconductor device including a pair of transistors.
2. Description of Related Art
A current mirror circuit and the differential input stage of an operational amplifier employ a pair of transistors, in which two transistors are arranged as a pair, in order to output an output current having a current value equivalent to or a certain times that of an input current.
In a case where MOS (metal oxide semiconductor) transistors configure the pair of transistors, the gates of both transistors are connected to each other and the sources are connected with a power source. In one of the transistors, the drain is connected with the gates of both the transistors. Hereinafter, the transistor whose drain is connected with the gates of both the transistors will be referred to as an input-side transistor, and the other transistor will be referred to as an output-side transistor.
Since the gates are connected to each other, when a drain current flows through the input-side transistor, the gate voltage of input-side transistor is applied to the gate of the output-side transistor and the drain current also flows through the output-side transistor and is output as the output current.
Here, even in a case of adopting a design so as to output an output current equivalent to or a certain times that of the input current, if the characteristics of the input-side and output-side transistors greatly vary, an error of the current value of the actually output current becomes large. Thus, characteristics of the transistors configuring the pair of transistors require a high ratio accuracy (relative accuracy).
JP2009-147881A discloses a current mirror circuit in which transistors connected in parallel to a power source via fuses are used as output-side transistors and trimming for adjusting the current value of an output current is performed by disconnecting the fuse.
JP2003-318278A discloses a mirror MOSFET including a mirror MOSFET structure in which two gate electrodes are formed in parallel in one active region, a source diffusion layer is formed in a region sandwiched by the two gate electrodes, and a drain diffusion layer is formed in a region opposite to the two gate electrodes with respect to the source diffusion layer. JP2003-318278A also discloses a current mirror circuit having a configuration in which two of the above mirror MOSFETs are arranged.
As described above, it is ideal that currents as designed flow through the transistors included in the pair of transistors. Achievement of this requires that characteristics of each transistor have a high ratio accuracy.
However, factors determining the characteristics of a transistor vary, depending upon the manufacturing process. Accordingly, the characteristics of the transistor also vary.
Here, since the drain current Id in a saturated region is represented by current Id∝μW/L·(Vgs−Vth)2, the factors determining the characteristics of the transistor include, for instance, a carrier mobility (μ), a channel length (L), a channel width (W) and a threshold voltage (Vth).
The factors determining the characteristics of the transistor also include a parasitic resistance.
According to the current mirror circuit disclosed in JP2009-147881A, the current value of the output current is adjusted by trimming, thereby reducing the error of the output current. According to the current mirror circuit disclosed in JP2003-318278A, the configuration in which two of the above mirror MOSFETs are arranged is adopted. This reduces variation in channel length, thereby reducing the error of the output current.
On the other hand, the inventor of the invention of this application has discovered that, as to the characteristics of the transistors in which high ratio accuracies are required, there is room to reduce the variations in characteristics owing to the parasitic resistance and the threshold voltage.
The variation in characteristics of the transistor owing to the parasitic resistance and the threshold voltage will hereinafter be described.
First, the variation in characteristics owing to the parasitic resistance will be described.
It is provided that, in a pair of transistors employed for a current mirror circuit or in the differential input stage of an operational amplifier, electrodes on a carrier supply side are set to a common potential. Hereinafter, it will be described such that the electrode on the carrier supply side is the source diffusion layer of the MOS transistor. Typically, in order to supply the diffusion layer with electricity, the diffusion layer and the wiring are connected to each other by a contact plug. In this case, there is contact resistance at the connection between the contact plug and the diffusion layer or the wiring. The contact resistance acts as parasitic resistance.
Variation in the contact resistances among transistors in which high ratio accuracies are required causes variation in characteristics of the transistors. Accordingly, the current value as designed cannot be achieved. Particularly, in a current mirror circuit, an output current with an output scaling factor as designed cannot be acquired.
Variation in the contact resistance further becomes obvious in a case where miniaturization of the semiconductor device increases the resistance of the contact plug itself.
Next, variation in characteristics owing to the threshold voltage will be described.
In some cases, in order to form a source/drain diffusion layer of the transistor, ion injection is applied to right and left regions of the gate electrode from an oblique direction with respect to the substrate. It is typically designed such that the source diffusion layer and the drain diffusion layer are symmetrical with each other. However, there is a case where the symmetry is reduced owing to oblique ion injection. In this case, a phenomenon may be caused in which the threshold voltage becomes different according to which one is employed as the source or the drain among the diffusion layers formed by the oblique ion injection. Variation in the threshold voltages among transistors in which high ratio accuracies are required causes the variation in characteristics of the transistors.